وظائف IMEC Inc

<p>Applied AI Scientist/Engineer About imec Qatar Imec Qatar is a new regional office where we drive our mission of pioneering innovative semiconductor solutions that lay the foundation for a smarter, greener, and truly AI-driven future. Specializing in advanced design tools for emerging technologies like silicon photonics and 3D integrated circuits, imec Qatar is at the forefront of chip development. We are also driving the future with intelligent solutions to optimize infrastructure and deep-tech innovations targeting applications for a sustainable society. This is more than just a new office - it is the start of an exciting journey. With the launch of imec Qatar, you have the unique opportunity to join us from day one and help shape the future of semiconductor innovation in the region. Be part of the team from the very beginning, joining us as Applied AI Scientist/Engineer in Doha, Qatar.</p><p><b><br></b></p><p><b>What you will do</b></p><p>You will contribute to the research, development, and application of AI techniques for semiconductor innovation within the newly launched imec Qatar center. Working as part of a multidisciplinary team of AI researchers, chip designers, and system architects, you will help advance the use of AI in ASIC design flows, compute architectures, and system-on-chip (SoC) development.</p><p>You will:</p><ul><li>Contribute to the execution of the AI roadmap for semiconductor R&amp;D activities within the center.</li><li>Collaborate with experts in AI, compute architectures, and chip design to explore and develop AI-enhanced methodologies for semiconductor design and optimization.</li><li>Help identify and evaluate high-impact application domains and use cases for AI-driven design flows, digital twins, and design automation in multiple application areas.</li><li>Contribute to the development of virtual twins of future compute platforms, enabling in-silico experimentation, architecture exploration, and validation of AI-optimized hardware components.</li><li>Develop, prototype, and evaluate AI methods that can accelerate or improve ASIC design, SoC architecture exploration, and hardware-software co-design workflows.</li><li>Work with AI-assisted design and co-design tools to enable intelligent optimization of semiconductor systems.</li><li>Share knowledge and collaborate closely with researchers, chip designers, and architects across multiple disciplines.</li><li>Contribute to publications, technical reports, demonstrations, and research proposals where appropriate.</li></ul><p><strong>Desired Candidate Profile</strong></p><p>Who you are</p><p>Required</p><ul><li>Master's or PhD in Computer Science, Electrical Engineering, Microelectronics, Computer Engineering, Applied Mathematics, or a related STEM field.</li><li>3+ years of experience in applied research and/or technology development involving AI, machine learning, or optimization methods.</li><li>Hands-on experience with one or more of the following: Reinforcement Learning Bayesian Optimization Graph Neural Networks (GNNs) Surrogate modeling Agentic AI systems Design-space exploration techniques</li><li>Strong programming skills in Python and familiarity with modern ML frameworks and software engineering best practices.</li><li>Experience developing proof-of-concepts and translating research ideas into prototypes, demonstrators, or deployable solutions.</li><li>Ability to work effectively in multidisciplinary R&amp;D teams.</li><li>Strong communication skills and an interest in collaborating with experts from both AI and semiconductor domains.</li></ul><p>Preferred</p><ul><li>Experience with semiconductor design flows, EDA tools, ASIC development, SoC architecture exploration, or computer architecture research.</li><li>Familiarity with hardware/software co-design methodologies.</li><li>Experience applying AI to engineering, scientific computing, optimization, or design automation problems.</li><li>Experience contributing to scientific publications, patents, or industrial research projects.</li><li>Knowledge of digital twins, simulation frameworks, or architecture modeling environments.</li><li>Experience mentoring junior colleagues, students, or project team members is a plus.</li></ul>

<p><br></p><p>What you will do As a DFT Engineer, you leverage your expertise in Design-for-Test to make cutting-edge integrated circuits optimally testable Working at the forefront of semiconductor technology, you play a pivotal role in ensuring the testability, quality, and performance of complex chip designs. You will:</p><ul><li>Architect DFT solutions for SOCs with multiple sub-blocks/partitions and complex soft/hard IPs with complex DFT requirements.</li><li>Coordinate/Negotiate DFT requirements.</li><li>Implement, and validate innovative DFT techniques on SOCs and sub-systems.</li><li>Define timing constraints for DFT test-modes.</li><li>Insert boundary scan, compression, MBIST/R(epair) and On-chip clock controllers for large-scale low-power designs in advanced nodes (5nm and beyond).</li><li>Generate test patterns, debug/improve fault coverage, support debug of post-silicon test patterns, diagnose memory and scan issues.</li><li>Work closely with the physical design team in the context of timing violations, signal/power integrity issues, routing congestion, etc.</li><li>Work closely with the test engineering team on silicon characterization and validation.</li><li>Adopt AI methodology to speed up all aspects of your work.</li></ul><p><strong>Desired Candidate Profile</strong></p><p>Who you are</p><ul><li>5+ years of experience with DFT insertion and ATPG.</li><li>Basic fluency with Verilog/VHDL to write code for test logic when needed.</li><li>Experience as a DFT owner of sub-systems including the insertion and verification of all DFT structures.</li><li>Experience with DFT integration of complex PHY blocks (such as PCIe, UCIe, LPDDR5, etc.).</li><li>Hands-on experience with defining SDC constraints for DFT, and inserting/verifying boundary scan, compression, MBIST/repair, OPCG/OCC, ATPG, fault coverage improvement, test debug, for large low-power designs in advanced nodes (5nm and beyond).</li><li>Expert knowledge in IEEE 1149.1, 1149.6, and 1687 (IJTAG) standards and associated file formats (ICL, PDL).</li><li>Preferably previous experience with defining/maintaining DFT flows.</li><li>Experienced in EDA tools such as Tessent (Siemens), Genus/Modus (Cadence), and simulation tools.</li><li>Experience using Tessent SSN is a plus.</li><li>Experience with the IEEE1838 standard and DFT for chiplets (2.5D/3D) is a plus.</li><li>Experienced in scripting languages, especially TCL.</li></ul>

<p>What you will do</p><p>As part of our multidisciplinary team, you will lead the research, development, and implementation of AI-driven solutions that advance semiconductor technologies and digital applications. Depending on your role and expertise, you will:&nbsp;</p><p><br></p><p>Plan and manage the AI skillset and resources across technology pillars.&nbsp;</p><p>Guide teams in achieving milestones for AI-driven projects.&nbsp;</p><p>Translate objectives into actionable research and development packages (e.g., AI-assisted codesign, digital twins, reinforcement learning).&nbsp;</p><p>Build, mentor, and manage cross-functional teams of AI scientists, engineers, and developers.&nbsp;</p><p>Establish robust pipelines for data acquisition, model training, and deployment.&nbsp;</p><p>Collaborate with internal and external stakeholders to embed and leverage AI in semiconductor platforms and system architectures.&nbsp;</p><p>Foster cross-disciplinary innovation and ensure AI supports next-generation technologies.&nbsp;</p><p>Manage project budgets, timelines, and reporting.&nbsp;</p><p>Represent the organization externally through publications, conferences, and academic engagement.</p><p>Who you are</p><p>Master’s or PhD in Computer Science, Electrical/Electronic Engineering, Applied Physics, Microelectronics, or a related STEM field.&nbsp;</p><p>5+ years of experience in applied research and/or development of AI applications, with leadership in areas such as reinforcement learning, Bayesian optimization, surrogate modeling, or agentic AI.&nbsp;</p><p>Demonstrable experience working in and/or leading effective, multidisciplinary teams.&nbsp;</p><p>Hands-on approach, contributing to the development of prototypes and proof-of-concept demonstrations.&nbsp;</p><p>Strong scientific programming skills, with experience in code documentation and repository management.&nbsp;</p><p>Proven leadership and project management capabilities.&nbsp;</p><p>Excellent communication skills; fluency in English required.&nbsp;</p><p>Familiarity or experience with R&amp;D of SoC architectures, ASICs design, or energy technologies is a plus.&nbsp;</p><div><br></div><p><strong>Desired Candidate Profile</strong></p><p><br></p>

<p>About imec Qatar Imec Qatar is a new regional office where we drive our mission of pioneering innovative semiconductor solutions that lay the foundation for a smarter, greener, and truly AI-driven future. Specializing in advanced design tools for emerging technologies like silicon photonics and 3D integrated circuits, imec Qatar is at the forefront of chip development. We are also driving the future with intelligent solutions to optimize infrastructure and deep-tech innovations targeting applications for a sustainable society. This is more than just a new office - it is the start of an exciting journey. With the launch of imec Qatar, you have the unique opportunity to join us from day one and help shape the future of semiconductor innovation in the region. Be part of the team from the very beginning, joining us as Physical ASIC Design Implementation Engineer in Doha, Qatar.</p><p>What you will do Imec s digital chip design team handles all steps from architecture to chip tapeout to the foundry. For the further extension of the physical digital implementation group, we are looking for a highly motivated engineer. The international team has an extensive industrial experience, contacts with leading industrial foundries, and long-standing relationships with all the main EDA tool vendors and IP providers. Imec also provides tapeout, prototype, fabrication and test services for advanced chips. As Physical ASIC design engineer, you will create GDSII files that can be sent to production from RTL or netlist. You will have full understanding of the complete Place&amp;Route flow: You will:</p><ul><li>Set up the flow for the specific library set and foundry node used</li><li>Set up low power design (UPF)</li><li>Floorplanning &amp; power grid design</li><li>Detailed Timing Driven Placement</li><li>STA &amp; possible design optimisation for setup</li><li>Clock Tree Synthesis</li><li>Scan chain re-stitching</li><li>Detailed Timing Driven Route (incl. SI)</li><li>IPO s (in-place optimization) to get the timing in all corners correct</li><li>Solve setup &amp; hold violations</li><li>Sign-off extraction</li><li>Sign-off timing</li><li>Sign-off Power analysis</li><li>Physical verification (DRC, ERC, LVS, ANT)</li><li>Logic equivalent check</li></ul><p>It it is an asset if you can take the lead for partitioning and split the top level SDC file into timing budget requirements/constraints of the sub-blocks for hierarchical design. You will work with other Physical Designers during the chip design cycle to drive signoff closure for tape-out. You are also looking out for AI methodology in the design flow to speed up all aspects of your work.</p><p><strong>Desired Candidate Profile</strong></p><p>Who you are You have a Master Degree in Electronics You have experience in hierarchical physical implementation in advanced nodes with either a Synopsys or Cadence EDA tool fow. You have experience in power reduction techniques like gated clocks, voltage domains, memory retention and switch off power domains. You have experience in debugging any tool/flow/design issues. You have excellent communication skills (English is a must) and can work within an international team.</p>